A quad transceiver, included in a DS1 interface telecommunications facility, receives an 8.192 Mbps data stream converted from four 1.544 Mbps data streams. One of the processing functions of the transceiver is input bit counting. Usually, the counter portion is formed on one chip device and the chip includes test function circuitry.
FIGS. 1A and 1B show a related art logic function circuit, which can be applied to such a counter portion with test function. The logic function circuit comprises M(=4) columns and N(=4) rows of logic circuits and flip-flops. Each logic circuit has an AND gate and an exclusive OR (XOR) gate to form a binary counter. Each row circuitry is connected so as to form a hexadecimal (2.sup.4) counter which separately counts the pulses of an input signal CI1, CI2, CI3 or CI4. Also, a multiplexer for mode selection is included between the respective logic circuit and flip-flop. The Q output terminal of each flip-flop is connected to an I1 input terminal of the respective multiplexer of the succeeding row. As well, the Q output terminal of each flip-flop of the fourth row is connected to the I1 input terminal of the first row multiplexer of the succeeding column. Clock pulses CLOCK are commonly fed to the clock input terminals of all flip-flops.
(i) OPERATION MODE
When a mode selection signal MS on a mode line 11 is logic "0", all multiplexers M11-M14, M21-M24, M31-M34 and M41-M44 select their I0 input terminals. The output signal from the XOR gate of each logic circuit is fed to the D input terminal of the associated flip-flop through the multiplexer. At the same time, the carry-out signal from the AND gate of each logic circuit is fed to the XOR gate of the succeeding logic circuit in that row. The output signal of each flip-flop is also fed to the XOR and AND gates of the associated logic circuit and to the AND gate of the succeeding logic circuit in that row. As a result, in response to the clock pulses CLOCK, the first, second, third and fourth row circuitry form identical hexadecimal counters to count pulses of input signals CI1, CI2, CI3 and CI4, respectively, on input lines 131-134. The hexadecimal counters provide carry-out signals CA1, CA2, CA3 and CA4 on output lines 151, 152, 153 and 154, respectively. Each hexadecimal counter provides its 4-bit logic states CO11, CO12, CO13, and CO14: CO21, CO22, CO23, and CO24: CO31, CO32, CO33, and CO34: and CO41, CO42, CO43, and CO44.
(ii) TEST MODE
In order for the logic function circuit to be in a test mode, the mode selection signal MS on the mode line 11 is switched to logic "1", so that all the multiplexers select their I1 input terminals. In the test mode, the output signal from each flip-flip is fed to the D input terminal of the succeeding flip-flop of that column through the multiplexer. Also, the output signal from each fourth row flip-flop is fed to the D input terminal of the first row flip-flop of the succeeding column.
A 16-bit data stream of a scan-in signal SI on a scan line 17 is provided to the flip-flop F11 through the multiplexer M11. In response to the clock pulses CLOCK, the 16-bit data stream of the scan-in signal SI is transferred through the flip-flops and its data is latched therein.
Thereafter, the logic state of the mode selection signal MS on the mode line 11 transits from "1" to "0". Accordingly, all multiplexers switch their selection to the I0 input terminals. 1-bit input signals CI1, CI2, CI3 and CI4 on the input lines 131-134 are provided. Each logic circuit acts on the 1-bit input signal data, the output data from the preceding logic circuits in that row, and the scanin signal SI bit data, which was latched into the associated flip-flop from the 16-bit data stream of the scan-in signal SI. The logic result of each logic circuit is latched to the associated flip-flop in response to the clock pulse CLOCK.
Thereafter, the logic state of the mode selection signal MS on the mode line 11 transits from "0" to "1". Another 16-bit data stream of scan-in signal SI on the scan line 17 is provided. In response to the clock pulses CLOCK, a bit stream of all resulting data latched into the flip-flops is read out in series from the output terminal of the flip-flop F44 at the fourth row and fourth column, and at the same time, the 16-bit data stream of the scan-in signal SI is transferred through the flip-flops and its data is latched therein.
Thereafter, the logic state of the mode selection signal MS on the mode line 11 is switched to "0". Again, 1-bit input signals CI1, CI2, CI3 and CI4 are provided to the input lines 131-134. Each logic circuit acts on another data, and its logic result is latched to the associated flip-flop in response to the clock pulse CLOCK.
Thereafter, the logic state of the mode selection signal MS on the mode line 11 transits to "1", and another 16-bit data stream of the scan-in signal SI is provided onto the scan line 17. In response to the clock pulses CLOCK, a stream of all the resulting data latched in the flip-flops is read out in series.
By repeating such steps and monitoring the resulting data which is read out from the flip-flop F44, it is possible to determine whether the logic circuits and flip-flops are operating properly.
In the related art logic function circuit, one multiplexer is required for testing each associated fli-flop. As a result, as many multiplexers are required as logic circuits and flip-flops.